Swinburne University of Technology
Faculty of Engineering and industrial Sciences
HET378 Integrated Circuit Design
Mini
Project 3
(a)
Design
of Dynamic RAM Controller
Design
a simplified dynamic RAM controller circuit
which has the following specifications:
The
inputs to the circuit are a 16 bit address (ADDRIN), a read signal (RD), a
write signal (WR), and an enable signal (EN). This circuit does not function
until EN becomes 1, then the 16-bit ADDRIN is loaded in as a row address (15
down to 8) and a column address ( 7 down to 0) registers. Also RD and WR
signals are “stored”. Subsequently, the row address is outputted at ( ADDROUT)
along with the row address strobe (RAS) signal which is generated one clock cycle later. Then, the column address is
outputted along with the column address strobe signal (CAS), which is generated
one clock cycle later. Finally, if the operation is a write operation ( RD = 0,
WR = 1), then the WE output is 1.Otherwise for a read operation ( RD = 1, WR =
0), the WE output remains 0. If RD and WR are both 1, then the controller
outputs the row address only. The controller returns to the initial state after
generating all the required signals.
Your submission should
include
1.
Source
code and test bench files along waveforms with comments added to verify the
functionality of design
2.
Synthesis
results and the estimated speed of the circuit
Make sure that your design does not contain
any unwanted latches.
(b) Design of Variable Delay
In pipelined computer systems, data marches in
streams. Since the stream can come from various sources, it is sometimes
necessary to delay one stream so that it arrives at the pipeline input at the
proper time. The following figure shown below which uses a two port memory is
used to delay a parallel data stream. In a two port memory, one can
simultaneously write to and read from the memory at the same time, provided
that the same memory location is not involved. The system works as follows: A
RESET initializes the device. When the START is asserted for one clock period,
the write address (WADDR) is initialized to 0 and the read address (RADDR) is
initialized to DELAY, the number of clock cycles that one wants the data
delayed. During the next clock period, the first data word is presented to the
memory input. For every clock pulse data is written and WADDR is incremented.
However, for the first DELAY clock pulses, RADDR is decremented and no reading
takes place. When RADDR reaches 0, reads begin and RADDR is incremented for
each clock pulse after that point. Thus, after the start up delay, DATA_OUT
will equal DATA_IN delayed by DELAY clock cycles. When STOP goes to 1 , the
system finishes the transmission of the remaining data stored in memory. Note
that this is a totally synchronous system. The two port memory can be viewed as
being a clocked register array. It can be assumed that the source providing the
data is also triggered of the same clock and that the START and STOP also
change with the clock.
(1) Develop a VHDL model description for the
controller and the two port memory. The controller should be able to delay the
input data from 0 to 15 clock pulses. The two port RAM should contain the
minimum number of locations required to support the delay. Use four bit data
words.
(2)
Simulate
the design for different delays.
(3) Synthesize
your design
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