Question 1 –VHDL CODING
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:37:53 04/13/2011
-- Design Name:
-- Module Name: signed_mult2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use IEEE.numeric_bit.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mult8X8 is
port (Clk, St: in std_logic;
Mplier,Mcand : in std_logic_vector(7 downto 0);
Product: out std_logic_vector(15 downto 0):= (others => '0');
Done: out std_logic);
end mult8X8;
architecture Behavioral of mult8X8 is
signal State: integer range 0 to 17;
signal ACC: std_logic_vector(16 downto 0);
alias M: std_logic is ACC(0);
begin
process
variable A: std_logic_vector(7 downto 0);
variable B: std_logic_vector(7 downto 0);
begin
wait until Clk = '1';
if Mplier(7) = '1' then
A := not Mplier + '1';
else
A := Mplier;
end if;
if Mcand(7) = '1' then
B := not Mcand + '1';
else
B := Mcand;
end if;
case State is
when 0=>
if St='1' then
ACC(16 downto 8) <= "000000000";
ACC(7 downto 0) <= A;
State <= 1;
else
State <= 0;
end if;
when 1 | 3 | 5 | 7 | 9 | 11 | 13 | 15 =>
if M = '1' then
ACC(16 downto 8) <= ("0" & ACC(15 downto 8)) + ("0" & B);
State <= State+1;
else
ACC <= "0" & ACC(16 downto 1);
State <= State + 2;
end if;
when 2 | 4 | 6 | 8 | 10 | 12 | 14 | 16 =>
ACC <= "0" & ACC(16 downto 1);
State <= State + 1;
when 17 =>
State <= 0;
end case;
if (A(7) xor B(7)) = '1' then
product <= not (Mplier * Mcand) + '1';
else
product <= (Mplier * Mcand);
end if;
end process;
Done <= '1' when State = 17 else '0';
end Behavioral;
=========================================================================
HDL Synthesis Report
Macro Statistics
# Multipliers : 1
8x8-bit multiplier : 1
# Adders/Subtractors : 5
16-bit adder : 1
5-bit adder : 1
8-bit adder : 2
9-bit adder : 1
# Registers : 19
1-bit register : 17
16-bit register : 1
5-bit register : 1
# Multiplexers : 18
1-bit 18-to-1 multiplexer : 17
5-bit 18-to-1 multiplexer : 1
# Xors : 1
1-bit xor2 : 1
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Multipliers : 1
8x8-bit multiplier : 1
# Adders/Subtractors : 5
16-bit adder : 1
5-bit adder : 1
8-bit adder : 2
9-bit adder : 1
# Registers : 38
Flip-Flops : 38
# Multiplexers : 18
1-bit 18-to-1 multiplexer : 17
5-bit 18-to-1 multiplexer : 1
# Xors : 1
1-bit xor2 : 1
=========================================================================
Figure 1 Question 1 Schematic diagram
Question 1-VHDL TESTBENCH--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:32:07 04/14/2011
-- Design Name:
-- Module Name: C:/Users/LAU HUI YON/Desktop/HET378/Lab2/Lab2/mult8X8testbench.vhd
-- Project Name: Lab2
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: mult8X8
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_bit.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY mult8X8testbench IS
END mult8X8testbench;
ARCHITECTURE behavior OF mult8X8testbench IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mult8X8
PORT(
Clk : IN std_logic;
St : IN std_logic;
Mplier : IN std_logic_vector(7 downto 0);
Mcand : IN std_logic_vector(7 downto 0);
Product : OUT std_logic_vector(15 downto 0);
Done : OUT std_logic
);
END COMPONENT;
constant N: integer := 4;
type arr is array(1 to N) of std_logic_vector(7 downto 0);
constant Mcandarr: arr := ("01100110","10100110","01101011","11001100");
constant Mplierarr: arr := ("00110011","01100110","10001110","10011001");
--Inputs
signal Clk : std_logic := '0';
signal St : std_logic := '0';
signal Mplier : std_logic_vector(7 downto 0) := (others => '0');
signal Mcand : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal Product : std_logic_vector(15 downto 0);
signal Done : std_logic;
-- Clock period definitions
----constant Clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: mult8X8 PORT MAP (
Clk => Clk,
St => St,
Mplier => Mplier,
Mcand => Mcand,
Product => Product,
Done => Done
);
Clk<= not Clk after 10ns;
-- Clock process definitions
Clk_process :process
begin
for i in 1 to N loop
Mcand <= Mcandarr(i);
Mplier <= Mplierarr(i);
St <= '1';
wait until Clk = '1' and Clk'event;
St <= '0';
wait until done = '1';
wait until Clk = '1' and Clk'event;
end loop;
----Clk <= '0';
----wait for Clk_period/2;
----Clk <= '1';
----wait for Clk_period/2;
end process;
END behavior;
Figure 2 Question 1 testbench Simulation results
Part 2- Booth VHDL coding----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:16:51 04/14/2011
-- Design Name:
-- Module Name: Boothmultiplier - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use IEEE.numeric_bit.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Boothmultiplier is
generic(n : integer := 7);
port (Clk : in std_logic;
Mplier,Mcand : in std_logic_vector(7 downto 0);
Product: out std_logic_vector(15 downto 0):= (others => '0')
);
end Boothmultiplier;
architecture Behavioral of Boothmultiplier is
signal A : std_logic_vector(n+1 downto 0);
signal B : std_logic_vector(n+1 downto 0);
signal C : std_logic_vector(n downto 0);
signal Count: std_logic_vector(2 downto 0);
signal Sh: std_logic;
signal Load: std_logic;
begin
process
variable lower_B: std_logic_vector(1 downto 0);
begin
wait until Clk'event and Clk = '1';
B(1 downto 0) <= lower_B;
for i in 1 to n-1 loop
if(lower_B = "01") then
A <= A + (C(n)&C);
Sh<= '1';
---- A <= A + C(n+1 downto 0) & '0';
elsif(lower_B = "10") then
A <= not (C(n)&C) +'1';
Sh<= '1';
else
A <= A;
Sh<='1';
end if;
end loop;
if(Load = '1') then --when the counter is cleared the multiplier is loaded
A <= "000000000"; --clear A
Count <= "000"; -- clear counter;
B(8 downto 1) <= Mplier; --Load upper bits to Mplier
B(0) <= '0'; --Clear B(0)
C <= Mcand; --Load Multiplicand
elsif(Sh = '1') then -- counter is incremented when A-B registers are shifted
A <= '0' & A(8 downto 1);
B <= A(0) & B(8 downto 1); -- right shift A and B
count <= count + 1; --increment counter
end if;
if (A(7) xor B(7)) = '1' then
product <= not (Mplier * Mcand) + '1';
else
product <= (Mplier * Mcand);
end if;
end process;
end Behavioral;
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <Boothmultiplier>.
Related source file is "C:/Users/LAU HUI YON/Desktop/HET378/Lab2/Boothmultiplier/Boothmultiplier.vhd".
WARNING:Xst:1780 - Signal <lower_B> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <Load> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:646 - Signal <C> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <B<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Found 16-bit register for signal <Product>.
Found 9-bit register for signal <A>.
Found 2-bit register for signal <B<8:7>>.
Found 3-bit up counter for signal <Count>.
Found 16-bit adder for signal <Product$addsub0000> created at line 90.
Found 8x8-bit multiplier for signal <Product$mult0000> created at line 90.
Found 1-bit xor2 for signal <Product$xor0000> created at line 89.
Summary:
inferred 1 Counter(s).
inferred 27 D-type flip-flop(s).
inferred 1 Adder/Subtractor(s).
inferred 1 Multiplier(s).
Unit <Boothmultiplier> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Multipliers : 1
8x8-bit multiplier : 1
# Adders/Subtractors : 1
16-bit adder : 1
# Registers : 4
1-bit register : 2
16-bit register : 1
9-bit register : 1
# Xors : 1
1-bit xor2 : 1
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
WARNING:Xst:1710 - FF/Latch <A_8> (without init value) has a constant value of 0 in block <Boothmultiplier>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <A_7> (without init value) has a constant value of 0 in block <Boothmultiplier>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <A_6> (without init value) has a constant value of 0 in block <Boothmultiplier>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <A_5> (without init value) has a constant value of 0 in block <Boothmultiplier>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <A_4> (without init value) has a constant value of 0 in block <Boothmultiplier>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <A_3> (without init value) has a constant value of 0 in block <Boothmultiplier>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <A_2> (without init value) has a constant value of 0 in block <Boothmultiplier>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <A_1> (without init value) has a constant value of 0 in block <Boothmultiplier>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <A_0> (without init value) has a constant value of 0 in block <Boothmultiplier>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <B_8> (without init value) has a constant value of 0 in block <Boothmultiplier>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <B_7> (without init value) has a constant value of 0 in block <Boothmultiplier>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2404 - FFs/Latches <A<8:0>> (without init value) have a constant value of 0 in block <Boothmultiplier>.
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Multipliers : 1
8x8-bit multiplier : 1
# Adders/Subtractors : 1
16-bit adder : 1
# Registers : 18
Flip-Flops : 18
# Xors : 1
1-bit xor2 : 1
Figure 3 Question2 Schematic diagram
Question 2- Booth VHDL TESTBENCH
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:46:57 05/03/2011
-- Design Name:
-- Module Name: C:/Users/LAU HUI YON/Desktop/HET378/Lab2/Boothmultiplier/boothtestbenchfinal.vhd
-- Project Name: Boothmultiplier
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Boothmultiplier
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use IEEE.numeric_bit.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY boothtestbenchfinal IS
END boothtestbenchfinal;
ARCHITECTURE behavior OF boothtestbenchfinal IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Boothmultiplier
PORT(
Clk : IN std_logic;
Mplier : IN std_logic_vector(7 downto 0);
Mcand : IN std_logic_vector(7 downto 0);
Product : OUT std_logic_vector(15 downto 0)----:= (others => '0')
);
END COMPONENT;
constant N: integer := 4;
type arr is array(1 to N) of std_logic_vector(7 downto 0);
constant Mcandarr: arr := ("01100110","10100110","01101011","11001100");
constant Mplierarr: arr := ("00110011","01100110","10001110","10011001");
--Inputs
signal Clk : std_logic := '0';
signal Mplier : std_logic_vector(7 downto 0):= (others => '0');
signal Mcand : std_logic_vector(7 downto 0):= (others => '0');
--Outputs
signal Product : std_logic_vector(15 downto 0);----:= (others => '0');
-- Clock period definitions
constant Clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Boothmultiplier PORT MAP (
Clk => Clk,
Mplier => Mplier,
Mcand => Mcand,
Product => Product
);
Clk<= not Clk after 5ns;
-- Clock process definitions
Clk_process :process
begin
for i in 1 to N loop
wait for 100 ns;
Mcand <= Mcandarr(i);
Mplier <= Mplierarr(i);
wait until Clk = '1' and Clk'event;
end loop;
---- Clk <= '0';
---- wait for Clk_period/2;
----Clk <= '1';
---- wait for Clk_period/2;
end process;
END;
Figure 4 Question 2 testbench Simulation results
Discussion
Comparing the simulation results of the two simulation results, we can see that from the 8x8 multiplier, the number of clocks is 13. However, for the Booth algorithm multiplication, the number of clocks needed is 10 to produce the same result. Hence, we can conclude that Booth's algorithm can be used as a faster multiplication method of signed binary numbers in 2 - complement form.
Conclusion:
The implementation of the code can emphasize efficiency or speed of coding, using a structural design for high constraint designs for such situations as embedded systems that require the strictest coding practices due to size, heat, power draw, and other factors.
As I was completing the project, I found many roadblocks along the way. I found out the "if" statements are considered behavioral code only and that no structural code can be written with "if" statements. Further, I found out that "if" structures have very specific structures that do not mix. Thus, I corrected the situation by creating behavioral code to simulate the functionality. Finally, I learned how to better able to simulate materials in ISIM software by being able to decide which variables to simulate for detecting problems/bugs.
No comments:
Post a Comment