Swinburne University of Technology
Faculty of Engineering and Industrial Design
HET378 Integrated Circuit Design
Min Project 2
Multiplier Design:Part 1
Design a multiplier that will multiply two 8-bit signed binary numberss to give a 16-bit product. A negative numbers should be represented in 2's complement form. Use the following method: First complement the multiplier and the multiplicand if they are negative, multiply the positive numbers, and complement the product if necessary. Design the multiplier so that the multiplications can be completed in the minimum number of clock cycles. Verify your design using the following cases
The objective of this part of the lab is to design and simulate a multiplier for signed numbers binary using Booth's algorithm. Negative numbers should be represented using by their twos complement. Booths algorithm works as follows assuming each number is n bits : Use an (n + 1) –bit register for the accumulator (A) so the sign bit will not be lost is an overflow occurs. Also, use an (n + 1)-bit register to hold the multiplier and an n-bit register (C) to hold the multiplicand.
- Clear A ( the accumulator), load into the upper n bits of B, clear B0, and load the multiplicand into C.
- Test the lower two bits of B (B1 B0).
- If B1 B0 = 01 , then add C to A ( C should be the sign-extended to n + 1 bits and added to A using an (n + 1)– bit adder).
- If B1 B0 = 10 , then add the twos complement of C to A
- If B1 B0 = 11 or 00 skip this step
4. Repeat steps 2 and 3 , n-1 more times
5. Product will be in A and B , ignore B0
- Draw a block diagram for the system. Use 9-bit register for A and B, a 9-bit full adder, an 8-bit complementer, a 3-b it counter, and a control network
- Develop VHDL code to describe
- Simulate your design using the following test cases
Report
Include VHDL code for both case with test benches and simulation results. Compare the performance of both designs
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